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EL8102, EL8103
Data Sheet August 10, 2007 FN7104.7
500MHz Rail-to-Rail Amplifiers
The EL8102, EL8103 represent single rail-to-rail amplifiers with a -3dB bandwidth of 500MHz and slew rate of 600V/s. Running off a very low 5.6mA supply current, the EL8102, EL8103 also feature inputs that go to 0.15V below the VSrail. The EL8102 includes a fast-acting disable/power-down circuit. With a 25ns disable and a 200ns enable, the EL8102 is ideal for multiplexing applications. The EL8102, EL8103 are designed for a number of general purpose video, communication, instrumentation, and industrial applications. The EL8102 is available in 8 Ld SOIC and 6 Ld SOT-23 packages and the EL8103 is available in a 5 Ld SOT-23 package. All are specified for operation over the -40C to +85C temperature range.
Features
* 500MHz -3dB bandwidth * 600V/s slew rate * Low supply current = 5.6mA * Supplies from 3V to 5.0V * Rail-to-rail output * Input to 0.15V below VS* Fast 25ns disable (EL8102 only) * Low cost * Pb-Free available (RoHS compliant)
Applications
* Video amplifiers * Portable/hand-held products
Ordering Information
PART NUMBER EL8102IS EL8102IS-T7 EL8102IS-T13 EL8102ISZ (Note) EL8102ISZ-T7 (Note) EL8102ISZ-T13 (Note) EL8102IW-T7 EL8102IW-T7A EL8102IWZ-T7 (Note) PART MARKING 8102IS 8102IS 8102IS 8102ISZ 8102ISZ 8102ISZ 4 4 BAVA PACKAGE 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 6 Ld SOT-23 6 Ld SOT-23 6 Ld SOT-23 (Pb-free) 6 Ld SOT-23 (Pb-free) 5 Ld SOT-23 5 Ld SOT-23 5 Ld SOT-23 (Pb-free) 5 Ld SOT-23 (Pb-free) PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027
* Communications devices
Pinouts
EL8102 (8 LD SOIC) TOP VIEW
NC 1 8 ENABLE 7 VS+ 6 OUT 5 NC
MDP0027
IN- 2
MDP0027 MDP0038 MDP0038 MDP0038 MDP0038
IN+ 3 VS- 4
+
EL8102 (6 LD SOT-23) TOP VIEW
OUT 1 6 VS+ 5 ENABLE +IN+ 3 4 IN-
EL8102IWZ-T7A BAVA (Note) EL8103IW-T7 EL8103IW-T7A EL8103IWZ-T7 (Note) 5 5 BAWA
MDP0038 MDP0038 MDP0038 MDP0038
VS- 2
EL8103IWZ-T7A BAWA (Note)
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
OUT 1 VS- 2
EL8103 (5 LD SOT-23) TOP VIEW
5 VS+
+IN+ 3 4 IN-
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003-2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL8102, EL8103
Absolute Maximum Ratings (TA = 25C)
Supply Voltage from VS+ to VS-. . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS+ +0.3V to VS- -0.3V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
Thermal Information
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +125C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION:Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = 5V, VS- = GND, TA = +25C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified. CONDITIONS MIN (Note 1) TYP MAX (Note 1) UNIT
DESCRIPTION
INPUT CHARACTERISTICS VOS TCVOS IB IOS TCIOS CMRR CMIR RIN CIN AVOL Offset Voltage Offset Voltage Temperature Coefficient Measured from TMIN to TMAX Input Bias Current Input Offset Current Input Bias Current Temperature Coefficient Common Mode Rejection Ratio Common Mode Input Range Input Resistance Input Capacitance Open Loop Gain VOUT = +1.5V to +3.5V, RL = 1k to GND VOUT = +1.5V to +3.5V, RL = 150 to GND OUTPUT CHARACTERISTICS ROUT VOP Output Resistance Positive Output Voltage Swing AV = +1 RL = 1k RL = 150 VON Negative Output Voltage Swing RL = 150 RL = 1k IOUT ISC (source) ISC (sink) Linear Output Current Short Circuit Current Short Circuit Current RL = 10 RL = 10 70 120 4.85 4.6 30 4.9 4.7 100 25 65 80 150 150 50 m V V mV mV mA mA mA 75 Common Mode VIN = 0V VIN = 0V Measured from TMIN to TMAX VCM = -0.15V to +3.5V 70 VS- -0.15 3.5 0.5 90 80 -9 -8 -0.8 3 -6 0.1 2 95 VS+ -1.5 0.6 +8 mV V/C A A nA/C dB V M pF dB dB
POWER SUPPLY PSRR IS-ON IS-OFF Power Supply Rejection Ratio Supply Current - Enabled Supply Current - Disabled VS+ = 4.5V to 5.5V 70 95 5.6 30 6 dB mA A
ENABLE (EL8102 ONLY) tEN tDS VIH-ENB VIL-ENB Enable Time Disable Time ENABLE Pin Voltage for Power-up ENABLE Pin Voltage for Shut-down 200 25 0.8 2 ns ns V V
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Electrical Specifications
PARAMETER IIH-ENB IIL-ENB VS+ = 5V, VS- = GND, TA = +25C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified. (Continued) CONDITIONS MIN (Note 1) TYP 8.6 0.01 MAX (Note 1) UNIT A A
DESCRIPTION ENABLE Pin Input Current High ENABLE Pin Input for Current Low
AC PERFORMANCE BW -3dB Bandwidth AV = +1, RF = 0, CL = 5pF AV = -1, RF = 1k, CL = 5pF AV = +2, RF = 1k, CL = 5pF AV = +10, RF = 1k, CL = 5pF BW Peak GBWP PM SR tR tF OS tPD tS dG dP eN iN+ iNNOTE: 1. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested. 0.1dB Bandwidth Peaking Gain Bandwidth Product Phase Margin Slew Rate Rise Time Fall Time Overshoot Propagation Delay 0.1% Settling Time Differential Gain Differential Phase Input Noise Voltage Positive Input Noise Current Negative Input Noise Current RL = 1k, CL = 5pF AV = 2, RL = 100, VOUT = 0.5V to 4.5V 2.5VSTEP, 20% to 80% 2.5VSTEP, 20% to 80% 200mV step 200mV step 200mV step AV = +2, RF = 1k, RL = 150 AV = +2, RF = 1k, RL = 150 f = 10kHz f = 10kHz f = 10kHz 500 AV = +1, RF = 0, CL = 5pF AV = +1, RL = 1k, CL = 5pF 500 140 165 18 35 1 200 55 600 4 2 10 1 15 0.01 0.01 12 1.7 1.3 MHz MHz MHz MHz MHz dB MHz V/s ns ns % ns ns % nV/Hz pA/Hz pA/Hz
Pin Descriptions
PIN EL8102IS 1 2 3 4 5 6 7 8 1 6 5 1 5 4 3 2 4 3 2 EL8102IW EL8103IW NAME NC ININ+ VSNC OUT VS+ ENABLE Not connected Inverting input Non-inverting input Negative power supply Not connected Amplifier output Positive power supply Enable and disable input FUNCTION
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FN7104.7 August 10, 2007
EL8102, EL8103 Simplified Schematic Diagram
VS+ I1 I2 Q5 R3 R1 IN+ Q1 Q2 R2 INDIFFERENTIAL TO SINGLE ENDED DRIVE GENERATOR Q3 Q4 Q8 R4 R5 VSR9 OUT R6 R7 VBIAS1 R8 Q7
Q6
VBIAS2
Typical Performance Curves
5 NORMALIZED GAIN (dB) VS = 5V AV = 1 RL = 1k CL = 5pF 5
3 GAIN (dB)
3 RF = RG = 1k 1 RF = RG = 2k
VOP-P = 200mV
1
-1
VOP-P = 1V
-1 VS = 5V AV = 2 RL = 1k CL = 5pF 1M
RF = RG = 500
-3
VOP-P = 2V
-3
-5 100k
1M
10M FREQUENCY (Hz)
100M
1G
-5 100k
10M FREQUENCY (Hz)
100M
1G
FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGE LEVELS
FIGURE 2. SMALL SIGNAL FREQUENCY RESPONSE vs RF AND RG
4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) VS = 5V CL = 5pF RL = 1k
4 VS = 5V CL = 5pF RL = 1k RF = 1k
2
AV = 2
AV = 1
2
AV = -1 AV = -5
0 AV = 5 -2 AV = 10
0
-2
-4
-4
AV = -10
-6 100k
1M
10M FREQUENCY (Hz)
100M
1G
-6 100k
1M
10M FREQUENCY (Hz)
100M
1G
FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS NON-INVERTING GAINS
FIGURE 4. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS INVERTING GAINS
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FN7104.7 August 10, 2007
EL8102, EL8103 Typical Performance Curves (Continued)
5 VS = 5V AV = 1 CL = 5pF VOP-P = 200mV 11 VS = 5V AV = 2 CL = 5pF RF = RG = 1k RL = 500
3 GAIN (dB)
9 RL = 100 RL = 1k GAIN (dB) 7
1
-1 RL = 500 -3
5
RL = 1k, 150
3
-5 100k
1M
10M FREQUENCY (Hz)
100M
1G
1 100k
1M
10M FREQUENCY (Hz)
100M
1G
FIGURE 5. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS RLOAD
FIGURE 6. SMALL SIGNAL FREQUENCY RESPONSE vs VARIOUS RLOAD
5 NORMALIZED GAIN (dB) VS = 5V AV = 1 RL = 1k VOP-P = 200mV CL = 10pF
11 VS = 5V AV = 2 RL = 1k RF = RG = 1k
CL=30pF CL = 20pF CL = 14pF
3 GAIN (dB)
9
CL = 5pF
1
7
-1
CL = 1.5pF
5
CL = 9pF CL = 5pF
-3
3
-5 100k
1M
10M FREQUENCY (Hz)
100M
1G
1 100k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 7. SMALL SIGNAL FREQUENCY RESPONSE vs CL
FIGURE 8. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS CL
110 RL = 1k 70 GAIN (dB) RL = 150
405
-10 VS = 5V AV = 1 RL = 1k
315 PHASE () GAIN (dB)
-30
30 RL = 150 -10 RL = 1k
225
-50
135
-70
-50
45
-90
-90 1k
10k
100k
1M
10M
100M
-45 1G
-110 1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 10. DISABLED OUTPUT ISOLATION FREQUENCY RESPONSE
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FN7104.7 August 10, 2007
EL8102, EL8103 Typical Performance Curves (Continued)
-10 550 500 -30 BANDWIDTH (MHz) PSRR (dB) PSRR450 400 350 300 250 200 -110 1k 10k 100k 1M 10M 100M 150 3.0 3.5 4.0 VS (V) AV = 2 4.5 5.0 5.5 RL = 1k CL = 5pF AV = 1
-50
-70
PSRR+
-90
FREQUENCY (Hz)
FIGURE 11. POWER SUPPLY REJECTION RATIO vs FREQUENCY
FIGURE 12. SMALL SIGNAL BANDWIDTH vs SUPPLY VOLTAGE
100
2.5 2.0 PEAKING (dB)
RL = 1k CL = 5pF
IMPEDANCE ()
10
1.5 1.0 AV = 2
AV = 1
1
0.1
0.5
0.01 10k
100k
1M FREQUENCY (Hz)
10M
100M
0 3.0
3.5
4.0 VS (V)
4.5
5.0
5.5
FIGURE 13. OUPUT IMPEDANCE vs FREQUENCY
FIGURE 14. SMALL SIGNAL PEAKING vs SUPPLY VOLTAGE
-15
10
-35 CMRR (dB)
8
IS (mA)
-55
6
-75
4
-95
2
-115 100k
0 1M 10M 100M 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 FREQUENCY (Hz) VS (V)
FIGURE 15. COMMON-MODE REJECTION RATIO vs FREQUENCY
FIGURE 16. SUPPLY CURRENT vs SUPPLY VOLTAGE
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FN7104.7 August 10, 2007
EL8102, EL8103 Typical Performance Curves (Continued)
-60 VS = 5V RL = 1k CL = 5pF AV = 2
HD2@10MHz
-70 -75 DISTORTION (dBc) -80 -85 -90 -95 VS = 5V f = 5MHz VO = 1VP-P FOR AV = 1 VO = 2VP-P FOR AV = 2
H D 3@ H D 3@
DISTORTION (dBc)
-70
HD2@
H D 2@
AV =2
HD2@5MHz
AV =1
-80
H @1M HD2
z
HD3@10M
Hz
-90
M Hz HD3@5
AV =2
HD3@1MHz
AV =1
-100 1 2 3 VO(P-P) (V) 4 5
-100 100 RLOAD ()
1K
2K
FIGURE 17. HARMONIC DISTORTION vs OUTPUT VOLTAGE
FIGURE 18. HARMONIC DISTORTION vs LOAD RESISTANCE
-50 VOLTAGE NOISE (nV/Hz) CURRENT NOISE (pA/Hz), VS = 5V RL = 1k CL = 5pF VO = 1VP-P FOR AV = 1 VO = 2VP-P FOR AV = 2
AV=2 HD2@
1k
-60 DISTORTION (dBc)
100 eN
-70
-80
HD2@AV=1
10 IN+ IN-
-90
HD3@AV=2
-100 1
HD
=1 3@AV
10 FREQUENCY (MHz)
40
1 10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 19. HARMONIC DISTORTION vs FREQUENCY
FIGURE 20. VOLTAGE AND CURRENT NOISE vs FREQUENCY
VS = 5V, AV = 1, RL = 1k TO 2.5V, CL = 5pF
VS = 5V, AV = 1, RL = 1k TO 2.5V, CL = 5pF
3.5
3.5
2.5
2.5
1.5
1.5
2ns/DIV
2ns/DIV
FIGURE 21. LARGE SIGNAL TRANSIENT RESPONSE - RISING
FIGURE 22. LARGE SIGNAL TRANSIENT RESPONSE - FALLING
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EL8102, EL8103 Typical Performance Curves (Continued)
VS = 5V, AV = 1, RL = 1k TO 2.5V, CL= 5pF VIN 5.0 VS = 5V, AV = 5, RL = 1k TO 2.5V
2.6 2.5 2.4
2.5 2.6 2.5 0 2.4 VOUT
10ns/DIV
2s/DIV
FIGURE 23. SMALL SIGNAL TRANSIENT REPONSE
FIGURE 24. OUTPUT SWING
VS = 5V, AV = 5, RL = 1k TO 2.5V
CH1
5.0
ENABLE INPUT
2.5
CH2
0
VOUT
2s/DIV
CH1, CH2, 1V/DIV, M=100ns
FIGURE 25. OUTPUT SWING
FIGURE 26. ENABLED RESPONSES
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 POWER DISSIPATION (W) 1.2 1.0 909mW 0.8 0.6 0.4 0.2 0 0 CH1, CH2, 0.5V/DIV, M = 20ns 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) SOT23-5/6 JA = +230C/W 435mW SO8 JA = +110C/W
ENABLE INPUT CH1
CH2 VOUT
FIGURE 27. DISABLED RESPONSE
FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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EL8102, EL8103 Typical Performance Curves (Continued)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.0 POWER DISSIPATION (W) 0.9 0.8 0.7 625mW 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) SOT23-5/6 JA = +256C/W 391mW SO8 JA = +160C/W
FIGURE 29. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Description of Operation and Application Information
Product Description
The EL8102, EL8103 are wide bandwidth, single supply, low power and rail-to-rail output voltage feedback operational amplifiers. Both amplifiers are internally compensated for closed loop gain of +1 of greater. Connected in voltage follower mode and driving a 1k load, the EL8102, EL8103 have a -3dB bandwidth of 500MHz. Driving a 150 load, the bandwidth is about 350MHz while maintaining a 600V/s slew rate. The EL8102 is available with a power-down pin to reduce power to 30A typically while the amplifier is disabled.
and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few pF range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. As far as the output stage of the amplifier is concerned, the output stage is also a gain stage with the load. RF and RG appear in parallel with RL for gains other than +1. As this combination gets smaller, the bandwidth falls off. Consequently, RF also has a minimum value that should not be exceeded for optimum performance. For a gain of +1, RF = 0 is optimum. For the gains other than +1, optimum response is obtained with RF between 300 to 1k. The EL8102, EL8103 have a gain bandwidth product of 200MHz. For gains 5, its bandwidth can be predicted by the Equation 1:
Gain x BW = 200MHz (EQ. 1)
Input, Output and Supply Voltage Range
The EL8102, EL8103 have been designed to operate with a single supply voltage from 3V to 5.0V. Split supplies can also be used as long as their total voltage is within 3V to 5.0V. The amplifiers have an input common mode voltage range from 0.15V below the negative supply (VS- pin) to within 1.5V of the positive supply (VS+ pin). If the input signal is outside the above specified range, it will cause the output signal to be distorted. The output of the EL8102, EL8103 can swing rail-to-rail. As the load resistance becomes lower, the ability to drive close to each rail is reduced. For the load resistor 1k, the output swing is about 4.9V at a 5V supply. For the load resistor 150, the output swing is about 4.6V.
Video Performance
For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150 because the change in output current with DC level. Special circuitry has been incorporated in the EL8102, EL8103 to reduce the variation of the output impedance with the current output. This results in dG and dP specifications of 0.01% and 0.01, while driving 150 at a gain of 2. Driving high impedance loads would give a similar or better dG and dP performance.
Choice of Feedback Resistor and Gain Bandwidth Product
For applications that require a gain of +1, no feedback resistor is required. Just short the output pin to the inverting input pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain
Driving Capacitive Loads and Cables
The EL8102, EL8103 can drive 10pF loads in parallel with 1k with less than 5dB of peaking at a gain of +1. If less peaking is desired in applications, a small series resistor (usually between 5 to 50) can be placed in series with the
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FN7104.7 August 10, 2007
EL8102, EL8103
output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: For sourcing, Equation 3:
V OUT PDMAX = V S x I SMAX + ( V S - V OUT ) x --------------R
L
(EQ. 3)
Disable/Power-Down
The EL8102 can be disabled and its output placed in a high impedance state. The turn-off time is about 25ns and the turn-on time is about 200ns. When disabled, the amplifier's supply current is reduced to 30A typically, thereby effectively eliminating the power consumption. The amplifier's power down can be controlled by standard TTL or CMOS signal levels at the ENABLE pin. The applied logic signal is relative to VS- pin. Letting the ENABLE pin float or applying a signal that is less than 0.8V above VS- will enable the amplifier. The amplifier will be disabled when the signal at ENABLE pin is 2V above VS-.
For sinking, Equation 4:
PD MAX = V S x I SMAX + ( V OUT - V S- ) x I LOAD (EQ. 4)
Where: VS = Total supply voltage ISMAX = Maximum quiescent supply current VOUT = Maximum output voltage of the application RLOAD = Load resistance tied to ground ILOAD = Load current By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat.
Output Drive Capability
The EL8102, EL8103 do not have internal short circuit protection circuitry. They have a typical short circuit current of 80mA sourcing and 150mA sinking for the output is connected to half way between the rails with a 10 resistor. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds 40mA. This limit is set by the design of the internal metal interconnections.
Power Supply Bypassing and Printed Circuit Board Layout
As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7F tantalum capacitor in parallel with a 0.1F ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces.
Power Dissipation
With the high output drive capability of the EL8102, EL8103, It is possible to exceed the +125C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 2:
T JMAX - T AMAX PD MAX = ------------------------------------------- JA (EQ. 2)
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Typical Applications
VIDEO SYNC PULSE REMOVER Many CMOS analog to digital converters have a parasitic latch up problem when subjected to negative input voltage levels. Since the sync tip contains no useful video information and it is a negative going pulse, we can chop it off. Figure 30 shows a gain of 2 connections for EL8102, EL8103. Figure 31 shows the complete input video signal applied at the input, as well as the output signal with the negative going sync pulse removed.
5V 1k VIN 75 + VS+ VS75 1k 1k 75 VOUT ENABLE 1k B 2MHz 1VP-P 75 -2.5V + +2.5V
-
1k 1k +2.5V A 2MHz 2VP-P 75 -2.5V +
75
VOUT
75
-
-
FIGURE 32. TWO TO ONE MULTIPLEXER
FIGURE 30. SYNC PULSE REMOVER
0V -0.5V ENABLE 1V VIN 0.5V 0V 1V VOUT 0.5V 0V M = 50ns/DIV A B -1.5V -2.5V 1V 0V -1V
FIGURE 33.
M = 10s/DIV
SINGLE SUPPLY VIDEO LINE DRIVER
FIGURE 31. VIDEO SIGNAL
MULTIPLEXER Besides the normal power-down usage, the ENABLE pin of the EL8102 can be used for multiplexing applications. Figure 32 shows two EL8102 with the outputs tied together, driving a back terminated 75 video load. A 2VP-P 2MHz sine wave is applied to Amp A and a 1VP-P 2MHz sine wave is applied to Amp B. Figure 33 shows the ENABLE signal and the resulting output waveform at VOUT. Observe the breakbefore-make operation of the multiplexing. Amp A is on and VIN1 is passed through to the output when the ENABLE signal is low and turns off in about 25ns when the ENABLE signal is high. About 200ns later, Amp B turns on and VIN2 is passed through to the output. The break-before-make operation ensures that more than one amplifier isn't trying to drive the bus at the same time.
The EL8102 and EL8103 are wideband rail-to-rail output op amplifiers with large output current, excellent dG, dP, and low distortion that allow them to drive video signals in low supply applications. Figure 34 is the single supply non-inverting video line driver configuration and Figure 35 is the inverting video line driver configuration. The signal is AC coupled by C1. R1 and R2 are used to level shift the input and output to provide the largest output swing. RF and RG set the AC gain. C2 isolates the virtual ground potential. RT and R3 are the termination resistors for the line. C1, C2 and C3 are selected big enough to minimize the droop of the luminance signal.
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EL8102, EL8103
5V RF 1k VIN RT 75 C1 47F R2 10k R1 10k + R3 C3 470F 75 C1 RG 47F 500 5V R3 C3 470F 75
VOUT
VIN RT 75
-
5V R1 10k 75
VOUT
+ 75
RG 1k
RF 1k C2 220F R2 10k C2 220F
FIGURE 34. 5V SINGLE SUPPLY NON INVERTING VIDEO LINE DRIVER
FIGURE 35. SINGLE SUPPLY INVERTING VIDEO LINE DRIVER
NORMALIZED GAIN (dB)
4 3 2 1 0 -1 -2 -3 -4 -5 -6 100K AV = -2 AV = 2
1M
10M
100M 500M
FREQUENCY (Hz)
FIGURE 36. VIDEO LINE DRIVER FREQUENCY RESPONSE
12
FN7104.7 August 10, 2007
EL8102, EL8103 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
13
FN7104.7 August 10, 2007
EL8102, EL8103 SOT-23 Package Family
e1 A N 6 4
MDP0038
D
SOT-23 PACKAGE FAMILY MILLIMETERS SYMBOL A A1 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX 0.05 0.15 0.05 0.06 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. F 2/07 NOTES:
E1 2 3
E
A2 b c
0.20 C
0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D
D E E1 e e1 L L1 N
0.15 C A-B 2X C D
1
3
A2 SEATING PLANE 0.10 C NX A1
1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only).
(L1)
H
6. SOT23-5 version has no center lead (shown as a dashed line).
A
GAUGE PLANE c L 0 +3 -0
0.25
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN7104.7 August 10, 2007

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